CPUFLAGS = -mthumb -mcpu=cortex-m3
CONFIG_ARCH = lpc175x
CONFIG_MCU = lpc1756
CONFIG_MCU_H = <arm/NXP/LPC17xx/LPC17xx.h>

CONFIG_MCU_FOSC = 8000000

CONFIG_MK2 = n
CONFIG_MK3 = y
CONFIG_MK3_STM32 = n

CONFIG_LD_SCRIPT     = lpc1756.ld
CONFIG_OPENOCD_CFG   = lpc175x.cfg
CONFIG_FLASH_START   = 0x0
CONFIG_FLASH_SIZE    = 0x40000
CONFIG_FW_FILE       = firmware.im3
CONFIG_FW_START      = 0xc000
CONFIG_FW_HEADERSIZE = 0x100
CONFIG_FW_MAGIC      = SNS3
CONFIG_CFGWARE       = ../verilog/sd2snes_mini/fpga_mini.bi3

DEBUG_FS         = n
DEBUG_SD         = n
DEBUG_SD_OFFLOAD = n
DEBUG_IRQ        = n
DEBUG_MSU1       = n
DEBUG_YAML       = n
DEBUG_USB        = n
DEBUG_USBHW      = n

MENU_FILENAME = "/sd2snes/m3nu.bin"

_PINMODE_ADDR(reg,b)    = (LPC_PINCON_BASE + offsetof(LPC_PINCON_TypeDef, PINMODE0) + ((((void*)reg - (void*)LPC_GPIO0) >> 2) + 4*(b>>4)))
_PINMODE_REG(reg,b)     = *(__IO uint32_t*)_PINMODE_ADDR(reg,b)

_PINMODE_OD_ADDR(reg)   = (LPC_PINCON_BASE + offsetof(LPC_PINCON_TypeDef, PINMODE_OD0) + (((void*)reg - (void*)LPC_GPIO0) >> 3))
_PINMODE_OD_REG(reg)    = *(__IO uint32_t*)_PINMODE_OD_ADDR(reg)

_PINSEL_ADDR(reg,b)     = (LPC_PINCON_BASE + offsetof(LPC_PINCON_TypeDef, PINSEL0) + ((((void*)reg - (void*)LPC_GPIO0) >> 2) + 4*(b>>4)))
_PINSEL_REG(reg,b)      = *(__IO uint32_t*)_PINSEL_ADDR(reg,b)

_FIO_SETCLR_ADDR(reg,val) = ((uint32_t)reg + offsetof(LPC_GPIO_TypeDef, FIOSET) + (!(val) * 4))
_FIO_SETCLR_REG(reg,val)  = *(__IO uint32_t*)_FIO_SETCLR_ADDR(reg,val)

GPIO_I = FIOPIN
GPIO_O = FIOPIN
SET_BIT(reg,b)        = reg->FIOSET = (0x00000001 << b)
CLEAR_BIT(reg,b)      = reg->FIOCLR = (0x00000001 << b)
OUT_BIT(reg,b,val)    = _FIO_SETCLR_REG(reg,val) = (0x00000001 << b),__DSB()
GPIO_DIR(reg,b,dir)   = reg->FIODIR = (reg->FIODIR & ~(1 << b)) | ((dir & 1) << b),GPIO_MODE_AF(reg,b,0)
GPIO_MODE_OUT(reg,b)  = reg->FIODIR |= (1 << b),GPIO_MODE_AF(reg,b,0)
GPIO_MODE_IN(reg,b)   = reg->FIODIR &= ~(1 << b),GPIO_MODE_AF(reg,b,0)
GPIO_MODE_AF(reg,b,af) = _PINSEL_REG(reg,b) = (_PINSEL_REG(reg,b) & ~(3 << (2*(b&15)))) | (af << (2*(b&15)))
GPIO_MODE_ANALOG(reg,b) =
GPIO_OPENDRAIN(reg,b) = BITBAND(_PINMODE_OD_REG(reg), b) = 1
GPIO_PUSHPULL(reg,b)  = BITBAND(_PINMODE_OD_REG(reg), b) = 0
GPIO_PULLUP(reg,b)    = _PINMODE_REG(reg,b) = (_PINMODE_REG(reg,b) & ~(3 << (2*(b&15))))
GPIO_PULLDOWN(reg,b)  = _PINMODE_REG(reg,b) = (_PINMODE_REG(reg,b) |  (3 << (2*(b&15))))
GPIO_PULLNONE(reg,b)  = _PINMODE_REG(reg,b) = (_PINMODE_REG(reg,b) & ~(3 << (2*(b&15)))) | (2 << (2*(b&15)))
GPIO_SPEED(reg,b,sp)  =

CONFIG_UART_NUM	         = 3
CONFIG_CPU_FREQUENCY     = 96000000
CONFIG_UART_PCLKDIV      = 1
CONFIG_UART_TX_BUF_SHIFT = 8
CONFIG_UART_BAUDRATE     = 921600
CONFIG_UART_DEADLOCKABLE = y

DEVICE_NAME = "sd2snes Mk.III"

# PLL0 96MHz
# Base clock:   8MHz
# Multiplier:   24
# Pre-Divisor:   1
# Divisor:       4
# => FCCO = 384MHz
# => CCLK = 96MHz
# => USBCLK = 48MHz

CONFIG_CLK_MULT         = 24
CONFIG_CLK_PREDIV       =  1
CONFIG_CLK_CCLKDIV      =  4
CONFIG_USB_DIV          =  8

SSP_CLK_DIVISOR         = 2

SNES_RESET_REG          = LPC_GPIO1
SNES_RESET_BIT          = 4

SNES_CIC_D0_REG         = LPC_GPIO1
SNES_CIC_D0_BIT         = 8

SNES_CIC_D1_REG         = LPC_GPIO1
SNES_CIC_D1_BIT         = 9

SNES_CIC_STATUS_REG     = LPC_GPIO1
SNES_CIC_STATUS_BIT     = 10

SNES_CIC_PAIR_REG       = LPC_GPIO1
SNES_CIC_PAIR_BIT       = 14

SNES_CIC_D0_MODEREG     = LPC_PINCON->PINMODE2
SNES_CIC_D0_MODEBIT     = 17

SNES_CIC_D1_MODEREG     = LPC_PINCON->PINMODE2
SNES_CIC_D1_MODEBIT     = 19


# FPGA pin mapping
# ================
# CCLK        P4.28 out
# PROG_B      P4.29 out
# INIT_B      P2.9  in
# DIN         P2.8  out
# DONE        P0.22 in

FPGA_CONF_EXT = "bi3"

FPGA_CCLKREG  = LPC_GPIO4
FPGA_CCLKBIT  = (28)

FPGA_PROGBREG = LPC_GPIO4
FPGA_PROGBBIT = (29)

FPGA_INITBREG = LPC_GPIO2
FPGA_INITBBIT = (9)

FPGA_DINREG   = LPC_GPIO2
FPGA_DINBIT   = (8)

FPGA_DONEREG  = LPC_GPIO0
FPGA_DONEBIT  = (22)

FPGA_SSREG   = LPC_GPIO0
FPGA_SSBIT   = (16)

FPGA_SEND_BYTE_SERIAL(data) = do {SET_FPGA_DIN(data); CCLK();\
 SET_FPGA_DIN(data>>1); CCLK(); SET_FPGA_DIN(data>>2); CCLK();\
 SET_FPGA_DIN(data>>3); CCLK(); SET_FPGA_DIN(data>>4); CCLK();\
 SET_FPGA_DIN(data>>5); CCLK(); SET_FPGA_DIN(data>>6); CCLK();\
 SET_FPGA_DIN(data>>7); CCLK();} while (0)

SET_FPGA_DIN(data)      = do {FPGA_DINREG->FIOPIN1 = data;} while (0)

FPGA_DIN_MASK()         = do {LPC_GPIO2->FIOMASK1 = ~(BV(0));} while (0)
FPGA_DIN_UNMASK()       = do {LPC_GPIO2->FIOMASK1 = 0;} while (0)

FPGA_MCU_RDY_REG        = LPC_GPIO2
FPGA_MCU_RDY_BIT        = 8

FPGA_CLKREG             = LPC_GPIO0
FPGA_CLKBIT             = 11

EMR_FPGACLK_EMCxTOGGLE  = (3<<6) /* EMC1TOGGLE */
MCR_FPGACLK_MRxR        = (1<<4) /* MR1R */
TMR_FPGACLK_MR          = LPC_TIM3->MR1
TMR_FPGACLK_DIV         = 5

QSORT_MAXELEM           = 2048
SORT_STRLEN             = 256
CLTBL_SIZE              = 100

DIR_FILE_MAX            = 16380

SPI_REGS     = LPC_SSP0
SPI_SR       = SR
SPI_PCLKREG  = PCLKSEL1
SPI_PCLKBIT  = 10
SPI_DMAID_TX = 0
SPI_DMAID_RX = 1
SPI_DMACH    = LPC_GPDMACH0

SPI_SCLKREG  = LPC_GPIO0
SPI_SCLKBIT  = 15

SPI_SSELREG  = LPC_GPIO0
SPI_SSELBIT  = 16

SPI_MISOREG  = LPC_GPIO0
SPI_MISOBIT  = 17

SPI_MOSIREG  = LPC_GPIO0
SPI_MOSIBIT  = 18

SD_HAS_WP = n

SD_DTREG   = LPC_GPIO0
SD_DTBIT   = (8)

SD_CLKREG  = LPC_GPIO0
SD_CLKBIT  = (7)

SD_CMDREG  = LPC_GPIO0
SD_CMDBIT  = (9)

SD_DAT0REG = LPC_GPIO2
SD_DAT1REG = LPC_GPIO2
SD_DAT2REG = LPC_GPIO2
SD_DAT3REG = LPC_GPIO2
SD_DAT0BIT = (0)
SD_DAT1BIT = (1)
SD_DAT2BIT = (2)
SD_DAT3BIT = (3)

SD_DAT_MASK()   = LPC_GPIO2->FIOMASK0 = ~0xf
SD_DAT_UNMASK() = LPC_GPIO2->FIOMASK0 = 0
SD_DAT_IN       = (SD_DAT0REG->FIOPIN0)
SD_DAT_OUT(x)   = (SD_DAT0REG->FIOPIN0 = x)

USB_CONNREG        = LPC_GPIO1
USB_CONNBIT        = 18
USB_VBUSREG        = LPC_GPIO1
USB_VBUSBIT        = 30
USB_DPLUSREG       = LPC_GPIO0
USB_DPLUSBIT       = 29
USB_DMINUSREG       = LPC_GPIO0
USB_DMINUSBIT       = 30

DAC_DEMREG = LPC_GPIO1
DAC_DEMBIT = 1

# LED connections Mk.III
# LED    color  IO    PWM     AF(PWM)
# -----------------------------------
# ready  green  P1.24 PWM1[5] 2
# read   yellow P1.23 PWM1[4] 2
# write  red    P1.20 PWM1[2] 2

LED_READY_REG         = LPC_GPIO1
LED_READY_BIT         = 24
LED_READ_REG          = LPC_GPIO1
LED_READ_BIT          = 23
LED_WRITE_REG         = LPC_GPIO1
LED_WRITE_BIT         = 20

LED_READY_PWM_AFNUM   = 2
LED_READ_PWM_AFNUM    = 2
LED_WRITE_PWM_AFNUM   = 2

LED_READY_PCRBIT      = 13
LED_READ_PCRBIT       = 12
LED_WRITE_PCRBIT      = 10

LED_READY_MRNUM       = 5
LED_READ_MRNUM        = 4
LED_WRITE_MRNUM       = 2

LED_READY_MR          = LPC_PWM1->MR5
LED_READ_MR           = LPC_PWM1->MR4
LED_WRITE_MR          = LPC_PWM1->MR2

HWREV0_REG = LPC_GPIO1
HWREV0_BIT = 31
HWREV1_REG = LPC_GPIO2
HWREV1_BIT =  4
HWREV2_REG = LPC_GPIO2
HWREV2_BIT =  6
HWREV3_REG = LPC_GPIO1
HWREV3_BIT = 15
HWREV4_REG = LPC_GPIO1
HWREV4_BIT = 28
HWREV5_REG = LPC_GPIO2
HWREV5_BIT =  7
HWREV6_REG = LPC_GPIO0
HWREV6_BIT = 10
HWREV7_REG = LPC_GPIO2
HWREV7_BIT =  5
